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2.6.14
JTAG Signals
Table 50. JTAG Timing
All frequencies
Characteristics
Symbol
Min
Max
Unit
TCK cycle time
TCK clock high phase measured at V M = 1.6 V
Boundary scan input data setup time
Boundary scan input data hold time
TCK fall to output data valid
TCK fall to output high impedance
TMS, TDI data setup time
TMS, TDI data hold time
TCK fall to TDO data valid
TCK fall to TDO high impedance
TRST assert time
t TCKX
t TCKH
t BSVKH
t BSXKH
t TCKHOV
t TCKHOZ
t TDIVKH
t TDIXKH
t TDOHOV
t TDOHOZ
t TRST
36.0
15.0
0.0
15.0
—
—
0.0
5.0
—
—
100.0
—
—
—
—
20.0
24.0
—
—
10.0
12.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.
Figure 38 shows the Test Clock Input Timing Diagram
t TCKX
t TCKH
TCK
(Input)
t TCKR
V M
V M
t TCKR
Figure 38. Test Clock Input Timing
Figure 39 shows the boundary scan (JTAG) timing diagram.
TCK
(Input)
t BSVKH
t BSXKH
Data
Inputs
Data
Outputs
t TCKHOV
Input Data Valid
Output Data Valid
t TCKHOZ
Data
Outputs
Figure 39. Boundary Scan (JTAG) Timing
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
63
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